The present disclosure relates to an electronic circuit, more particularly relates to a charge pump circuit with dynamic current biasing for a fast locked phase locked loop circuit.
Phase locked loop (PLL) circuit plays important role in generating clock signals and other synchronized timing signals in electronic systems. PLL circuits are widely used in areas ranging from PC motherboard clock generator to wireless transceiver frequency synthesizer. Almost all applications require the PLL to be turned on and locked fast. For example, in a typical microcontroller with PLL integrated inside, the faster the PLL to lock, the faster the microcontroller can respond to system. People can always easily switch from one clock source to PLL clock without waiting a long time due to long locked time for the PLL. Thus, a PLL with a faster lock-in rate can give an end-product better performance and much more user-friendly. Lock-in time, TL, is thus a critical parameter for a PLL circuit. TL is defined as the time required for a PLL to lock from the un-locked state.
As such, circuit designers always sought to reduce the lock-in time in PLL circuits. As described in “Phase-Locked Loops: Design, Simulation, and Applications” by Roland E. Best, published by McGraw-Hill Professional; 5th edition, 2003, the lock-in time TL can be defined using the following equation:TL=(2×π)/ωN  (1)where ωN, the natural frequency of the PLL circuit, can be expressed by the following equation:ωN=sqrt ((KCP×KVCO))/(N×C2))  (2)where KCP is charge-pump gain that equals to the charge pump current; KVCO is voltage-controlled-oscillator (VCO) gain that is defined as the slope of the VCO frequency against VCO voltage. KCP has a unit of μA. KVCO has a unit of MHz/V. N is a feedback divider coefficient, which is usually an integer number. C2 is the capacitance of a capacitor C2 in the loop filter (FIG. 2).
Substituting (1) into (2), we obtain:TL=(2×π)/sqrt ((KCP×KVCO)/N×C2))  (3)
The equation (3) shows that TL can be reduced by an increase either KCP or KVCO or a decrease N or C2.
Furthermore, a phase jitter noise bandwidth BL can be defined asBL=(ωN/2)×(ζ+1/4ζ)  (4)where ζ is the damping factor of the PLL. Equations (1) and (4) show that the lock-in time and the phase jitter noise bandwidth follow opposite trends as a function of ωN. As ωN increases, the lock-in time decreases, but the phase jitter noise bandwidth increase, that is, more jitter are introduced into the electronic system. There is therefore a need for reducing the lock-in times in PLL circuits while minimizing the jitter noise in the system.